In the past, base-stations would be provided with a small cabinet at the base of the antenna tower, in which appropriate equipment to perform all base-station functions was provided. Thus each antenna would have its own dedicated equipment for both the RF functions and the baseband functions. However, newer generations of radio base station systems use a split into sub-systems so that the baseband functions are separated from the RF functions and provided in another subsystem.
The baseband subsystem is typically in a cabinet or other housing, and connected to a remote RF subsystem via an optical fiber of suitable length or other, e.g. wired, link suitable to transport signals over a long distance (typically the baseband and RF subsystem are separated by a distance of 1 km or more, e.g. >10 km). The remote RF subsystem is housed in what is commonly referred to as a “radio head” which further contains the antenna. Furthermore, the baseband subsystem may be connected to several antennas separated from each other by relatively long distances (>1 km or more, e.g. >10 km) and control the RF subsystems of multiple radio units. The radio-heads of several spaced-apart antennas are thus simultaneously controlled by the same base-station, located at a distance from the radio-heads.
In such new generations of base-stations, multiple radio equipment controller (REC) units and/or radio equipment (RE) units may be coupled in a chain, while such a chained unit may process part of the data samples and/or control data and forward a further part to a subsequent unit. The units may have, for interfacing between the units, a data interface for streaming data samples using a transmit clock. The clocks of the subsystems of the chain typically need to be synchronized with high precision. For example both the Open Base Station Architecture Initiative (OBSAI) and the Common Public Radio Interface (CPRI) require such high accuracy synchronization.
The standard “Common Public Radio Interface (CPRI); Interface Specification V5.0 (2011-09-21)”, hereinafter CPRI 5.0, describes an example of the interface, abbreviated as CPRI. The CPRI configuration may have multiple baseband subsystems, called Radio Equipment Controllers (REC), and/or multiple RF subsystems, called Radio Equipments (RE), connected point to point in a chain network using very high frequencies (up to 9.8304 GHz in CPRI V5.0) for streaming interfacing. Data samples are received at the RE and interfaced to the REC via an IQ data link called a lane, in a data format based on the I and Q components of the modulated signal. Besides IQ data link, CPRI supports further types of communication and management (C&M) data: a Vendor Specific (“VSS”) channel, a High-Level Data Link Control, HDLC, (“slow C&M channel”) and an Ethernet link (“fast C&M channel”).
According to the CPRI standard the Radio Equipment Controllers (REC) and Radio Equipment (RE) may be connected to each other via the CPRI interface point to point or in a chain. Several speeds are defined for the CPRI links and the highest speed in CPRI V5.0 is 9.8304 GBaud. Two, in the logical network structure (so not necessarily physically), neighboring devices are coupled to each other via a CPRI connection of which one part is defined as a master port and the other port is defined as the slave port.
The device at the slave port has to synchronize to the master port for all link rates. CPRI defines very strict synchronization requirements and it should be possible synchronize over, e.g., a distance of up to 40 km. For example, requirement R-18 of CPRI 5.0 recites: “Maximum contribution of Δf/f0 of jitter from the CPRI link to the radio base station frequency accuracy budget (between master SAPS and slave SAPS) is ±0.002 ppm”. Requirement R-18 also imposes that each slave port receives a clock signal traceable to the clock of the Radio Equipment Controller acting as synchronization master (of, for example, the chain of devices). When the devices are coupled in a chain, the master REC device provides its clock signal to the neighboring (RE or slave REC) device (e.g., for CPRI directly connected to the master port(s) of the master REC device). The neighboring device generates an internal clock signal that is based on the received clock signal of the master REC, and this generated internal clock signal may be provided to a subsequently neighboring (RE) device.
FIG. 1 shows a prior art CPRI system which comprises a master REC 110, which is an example of a synchronization master, and a synchronization slave device 150, such as a slave REC or a slave RE. A distance between the master REC 110 and the slave device 150 may be more than 10 Km, but the master REC 110 and the slave device 150 may also be located at the same location but at, for example, other boards of the base station. The master REC 110 and the slave device 150 are connected to each other via a CPRI links 102, which are bidirectional and allow to transmit data from the master to the slave, as indicated with “CPRI Tx”, or vice versa, as indicated with “CPRI Rx”. Slave device 150 may also be coupled by a further CPRI link 192 to a subsequent slave device (not shown). The subsequent slave device may be a RE and may have a similar architecture as slave device 150.
The master REC 110 receives from a separate oscillator 112 a signal which is used to generate the transmission clock signal Tx Clk. The master REC device generates the clock signal Tx Clk on basis of its internal oscillator PLL. The transmission clock signal Tx Clk is provided to the CPRI circuitry and to a SerDes circuitry 118 which transmits a signal such that the slave device 150 can use the received signal to synchronize to the Tx Clk signal of the master REC 110. A SerDes circuitry transforms the received serial signal into a parallel signal and transforms the internally generated parallel signals into a serial signal. In the slave device 150, as a termination point of the CPRI link 102, also a SerDes circuitry 158 is provided. The SerDes circuitry 158 generates on basis of the received signal the Clock Data Recovery clock signal Rx CDR which is used in the SerDes circuitry 158 to de-serialize/demodulate the received CPRI signal such that the SerDes circuitry 158 can provide a received parallel CPRI signal to the CPRI core circuitries. The slave device 150 has also an input port to which an output signal of a separate oscillator OSC, 152 must be provided to generate the internal transmission clock signal Tx Clk which has approximately the frequency of the CPRI link 102. The Tx Clk signal is provided to a subsequent SerDes circuitry 168 of the slave device 150 such that a correct CPRI signal may be generated for the subsequent CPRI link 192.
The internal transmission clock signal Tx Clk is generated by a PLL connected to the input port. As mentioned, this Tx Clk signal generated in the slave device 150 must fulfill various synchronization and jitter requirements. Common Phase Locked Loops (PLL) have a jitter accuracy of ±200 ppm, whereas ±0.002 ppm is required. To achieve the very strict synchronization requirements, the (slave) (RE) devices thus have to use an external jitter cleaner PLL (JCPLL) that is provided in between the oscillator of the port of at which the (slave) (RE) device expects to receive the oscillator signal. The JCPLL also receives from the device a receiver clock signal which is the internal clock used by the receiver of the device to de-serialize and/or demodulate the signals from the master device.
As shown in FIG. 1, the oscillator OSC, 152 is not directly coupled to the input port, but an external jitter cleaner PLL 154, JCPLL is coupled between the oscillator OSC, 152 and the input port. Furthermore, the Clock Data Recovery clock signal Rx CDR is provided to a frequency divider 160 which brings the frequency of the Clock Data Recovery clock signal Rx CDR towards the frequency of the oscillator OSC, 152 and the divided Clock Data Recovery clock signal is provided to the jitter cleaner PLL 154, JCPLL. Internally, in the SerDes circuitry 158, the signal received from the jitter cleaner PLL 154, JCPLL is also used to generate the Clock Data Recovery clock signal Rx CDR. In this way the Jitter cleaner PLL 154, JCPLL is able to create a clock signal at the (clock) input port of the SerDes circuitry 158 such that all internal clocks of the slave device 150 are well synchronized to the transmission clock signal Tx Clk of the master REC 110 without the introduction of too much jitter.
However, the external jitter cleaner is costly, typically in the order of 10 to 20 USD and increases the footprint of the device. Also, when using an external jitter cleaner, the board designer has to integrate all the components and test them.